1. Field of the Invention
The present invention relates to a Power Integrated Circuit ("PIC") structure featuring a Vertical Insulated Gate Bipolar transistor (IGBT) power stage, and to a manufacturing process thereof.
2. Discussion of the Related Art A "Power Integrated Circuit" ("PIC") is a monolithic integrated structure comprising one or more power parts ("a power stage") and a driving, control and protection circuit.
Several efforts have been made to obtain PICs with a minimum increase in the fabrication process complexity. Examples are given in the documents listed below, each of which is incorporated herein by reference:
1) J. P. Mille, Proceedings of Symposium on HV & Smart Power ICs, Los Angeles, May 1989, p. 517-525, PA1 2) F. Goodenough, Electronic Design, Mar. 4. 1993, p. 27-28,
where manufacturing processes are described for obtaining PICs featuring a vertical Double-diffused MOSFET ("VDMOSFET") and/or an NPN bipolar junction transistor power stage. The driving and control circuitry comprises N-channel MOSFETs (both enhancement- and depletion-mode); the N-channel MOSFETs of the driving and control circuitry are provided in a P type well diffused in the lightly doped N type epitaxial layer constituting, together with a heavily doped N+ silicon susbtrate, the VDMOSFET drain; the electric isolation of the driving and control circuitry from the power stage is achieved by reverse biasing the P type well/N type epitaxial layer junction (this technique is known as self-isolation).
With respect to the VDMOS manufacturing process, these structures require only the addition of a few steps, such as the definition of the P type well and of the depletion implant.
A Vertical IGBT could be integrated simply by starting the process with a P+ silicon substrate, instead of an N+ substrate, as it happens in discrete power pares.
Actually, this is a superficial approach; it is in fact known that the IGBT structure inherently includes a pair of parasitic NPN and PNP transistors connected to form a Silicon Controlled Rectifier ("SCR"); if the parasitic SCR turns on (latch-up), the PIC can malfunction and even be permanently damaged. To prevent the latch-up, the base region of the NPN parasitic BJT (i.e. the body and deep body regions of the IGBT elementary cells) is heavily doped (to reduce the gain) and is short-circuited to the emitter region (which coincides with the source regions of the IGBT elementary cells). Pairs of NPN and PNP parasitic BJTs are also associated with each N-channel MOSFET in the driving and control circuitry of the PIC; in this case the base region of the NPN parasitic BJT coincides with the P type well, which has a doping much lighter than the body and deep body regions of the IGBT elementary cells, thus the gain of the parasitic NPN is much higher, and the latch-up is harder to prevent.
In view of the state of the art just described, an object of the present invention is the integration of a Vertical IGBT in a PIC structure with driving and control circuitry comprising at least N-channel MOSFETs, overcoming at least the above mentioned drawbacks.